1. Technical Field
This disclosure discloses a non-volatile memory, in particular, to a non-volatile memory component and a method for manufacturing a floating gate by employing a damascene trench formed by an erase gate (EG) and a select gate (SG).
2. Related Art
Split-gate non-volatile memory components are widely applied on independent and embedded non-volatile application. Because of it has the features that smaller sector erasure and easy circuit design support, split-gate become more and more important in the IC industry.
About the split-gate non-volatile memory components technology in the market, such as the double-polysilicon split gate, which is well-approved by end-users because of its reliable stability and produce easily, of Microchip and SST company. This technology employs two polysilicon layers. The first polysilicon is the floating gate (FG) while the second polysilicon is the select gate. However, the dimension of IC device become more and more small, but double-polysilicon needs large area for the diffusion of source region and floating gate coupling. The double-polysilicon split gate will not meet the dimension diminution requirement in the near future.
The spilt-gate memory dimension can be scaled down by adding an additional polysilicon layer to form a coupling gate (for example, control gate), so the three-layer-polysilicon split-gate becomes more and more important. This technology employs three polysilicon layers; the first polysilicon is the floating gate (FG). The second polysilicon is the control gate while the third polysilicon is the erase gate (EG)/select gate (SG).
Similar to the well-known stack-gate non-volatile memory components (for example, ETOX), a floating gate (FG) is set in the bit-line direction at first, and then a control gate (CG) is formed and use it as a mask for etching floating gate (FG). The spacer between the erase gate (EG) and the select gate is formed by etching the third polysilicon, and the erase gate (EG) and the select gate (SG WL) are formed at the same time. The manufacture process integration of the transistor oxide layer of the select gate (EG) and the select gate (SG WL) needs to be dealt with carefully because there are gate dielectric layers for different purposes.
Unfortunately, it is hard to achieve the above mentioned requirements in the existed methods of the split-gate structure formation. The insulation dielectric layer between the floating gate (FG) and the select gate (SC) need to be integrated in the composition of the insulation tunneling oxide layer, and it will caused that the process become complex and inflexible. The process of the existed tri-polysilicon spilt gate need to employ etching process and the oxide layer growth of the rough polysilicon surface of the floating gate (FG), which forms the erase node. If the polysilicon surface and the tunneling oxide layer do not be dealt with well in the process, an unexpected reliability issue of the tunneling oxide layer will be induced by the uneven micro structure of the floating gate (FG) surface.